1. Field
The invention relates generally to the integration of multiple integrated circuit memory chips combined into a memory module. In particular, the invention relates to a memory module including memory chips, an optical interface, and a proximity communication system linking them.
2. Related Art
Computer systems today suffer from a disparity between processing power and bandwidth to memory. On-chip processing performance has improved by about 40% per year over the past two decades due to increased transistor counts and speeds enabled by lithographic scaling of transistor dimensions. In contrast, off-chip bandwidth to main memory has increased much more slowly, at about 10% per year over this timeframe, due to limited improvements in package pin count, board wiring density, and channel speeds. The technical challenge to reducing this gap in performance lies in increasing the bandwidth to main memory.
This problem exists in general for all high performance computer systems, but the problem is acute in multi-core processors. In these processors, a single chip executes tens of software threads simultaneously. Bandwidth improvements are critical to prevent these threads from having to wait on memory accesses from the different threads. In addition, multi-core processors require a much larger memory space than single-core processors to support simultaneous execution of many independent threads. Existing memory modules present challenges in scaling to hundreds of gigabytes of memory due to difficulties in interfacing the memory modules to a memory controller.
Existing memory module technologies, such as double-data-rate-2 (DDR2) or double date rate-3 (DDR3) dual in-line memory modules (DIMMs), typically include a memory interface chip and multiple memory chips, usually dynamic random access memories (DRAMs), mounted on a small printed circuit board including electrical interconnections formed in the board. Such modules, however, are limited by the number of wiring channels and connectors, power, and bandwidth in the printed circuit boards.
Technologies that overlay serial links on these channels, such as fully buffered DIMMs (FBDIMMs) and Rambus memory modules, improve electrical signaling performance per channel, but are still limited by board or cable wiring channels, and by electrical tradeoffs in bandwidth versus power and bandwidth versus distance. It is possible in an optical fully buffered module to replace the electrical interface with an optical interface between the memory controller and the memory modules. Optical communication provides welcome improvement in power and bandwidth metrics for this interface but can easily exceed the I/O bandwidths of memory chips in the module limited by conventional pin-oriented connections.
The bandwidth of conventional designs of memory modules is limited by a number of factors. For example, the number of parallel electrical interconnects, that is, the bus width, in the printed circuit board between the interface and the multiple memory chips is limited by the pitch of parallel connectors in the lines, currently limited to a pitch of 140 to 190 microns. The limited number of interconnections has prompted the design of a typical DRAM chip to include a single I/O port for multiple memory banks on the chip, only one of which can be accessed during a memory cycle.
Accordingly, it is desired to match the internal bandwidth of the memory module with the large external bandwidth provided by optical channels.